1. Field of the Invention
This invention relates to a testable programmable logic array (a testable PLA) which is an important component used in semiconductor integrated circuits, including logic VLSIs, and more particularly, to a testable PLA in which a testing circuit is incorporated whereby devices formed at crosspoints of input lines and output lines in an AND plane and an OR plane are tested with a high coverage of crosspoint faults, which are characteristic faults of the PLA, and which is provided within a reasonable excess area increase and a suitable number of test cycles.
2. Description of the Prior Art
Recently, a Programmable Logic Array (hereinafter referred to as PLA) has become recognized as a device which is one of the most important logical blocks applicable to VLSI design, by which the VLSI can be easily implemented so that a required logical function is provided at a high density.
In general, a PLA with n inputs and m outputs, as shown in FIG. 1, comprises an n-bit 1-to-2 decoder 1 for producing a literal (xi and xi) from input xi (i=1 to n=5 in FIG. 1), an AND plane 2 for implementing product terms as a product part of an arbitrary logical function defined by logical AND (product) operations and logical OR operations, and an OR plane for implementing OR terms as an OR part of the logical function. In the AND plane 2, there are input lines and product term lines yj (j=1, . . . , p; p=12 in FIG. 1) which are vertical to the input lines. The output lines of the decoder 1 are connected to the input lines (hereinafter referred to as literal input lines) of the AND plane 2. The product term lines of the AND plane are also used as the output lines of the AND plane 2. The product term lines are connected to the input lines of the OR plane 3. In addition, output lines zk (k=1, . . . , m; m is 3 in FIG. 1), are also provided vertical to the input lines yi or the product term lines and the outputs f1 to f3 of the PLA to external devices through inverters 17 or drivers are provided in front of the output lines Zi. In this explanation, the crosspoints in the AND plane 2 and the OR plane 3 are formed from MOS transistors, which are described later in detail in this section. The product terms and OR terms in the logical functions for the PLA are realized according to whether or not a device is formed on each crosspoint.
Hereinafter, throughout this specification, a cross point is referred to as a real crosspoint when a device such as a MOS transistor is formed on the crosspoint. Conversely, a crosspoint is referred to as an empty crosspoint when no device is formed on the crosspoint.
With reference to FIG. 1, we will now explain the basic operation of a most conventional PLA and a test method in which a NMOS is formed as an element of a real crosspoint. In the subsequent embodiment according to the present invention, we will describe a test method for testing a testable PLA with a test circuit according to the present invention.
First, as shown in FIG. 1, each of the actual cross points, which are designated as black triangle marks on the PLA, has a configuration, as shown in FIG. 2. When a high level voltage (hereinafter defined as logical "1", and designated simply as "1") is provided to a real crosspoint, as shown in FIG. 2, a NMOS transistor as the real crosspoint enters the ON state electrically, the output of the NMOS becomes a low level voltage (hereinafter defined as logical "0"). Conversely, when logical 0 is applied to the input "In" of the real crosspoint, the NMOS enters the OFF state.
In this case, the logical value of the output of the real crosspoint cannot be determined by the input "In", and all real crosspoints on an output line, including this real crosspoint, make the output logical 1 when all these real crosspoints enter the OFF state. The product term lines yj (j=1, . . . , p) and the output lines zk (k=1, . . . , m) such as the above output line are connected to load circuits 15 and 16, respectively, as shown in FIG. 1, and electrical charge from the load circuits 15 and 16 is stored in these product term lines yi and the output lines zk only when all real cross points on each of these lines yi and zk are on the OFF state. Consequently, the output of each line enters the logical 1 state. For example, the product term line y2 outputs logical 1 when the input data (x1,x2,x3,x4,x5) is (x,0,x,0,0), where x denotes "don't care". As a result, the real crosspoint on the input line y2 in the OR plane 3 enters the ON state, resulting in z2=0. That is, the output f2 of the OR plane 3 becomes logical 1. With input data other than that described above, the product term line y2 is logical 0, so that it cannot determine the value of the final output f2 of the PLA, namely the output f2 of the OR plane 3. There is no real crosspoint between the product term line y2 and the output lines z1 and z3, so that the value of the output lines z1 and z3 cannot be affected by the value of the product term line y2. As a final explanation of the conventional PLA operation, the Boolean expression of the logical function f2 in FIG. 1 is shown in the following: ##EQU1##
The PLA is very suitable for designing a VLSI, as described above, however, it is well known by a person skilled in the art pertaining to the PLA that there are many problems in testing the PLA operation, due to the following reasons:
(1) Both the AND plane and the OR plane of a PLA are Large fan-in logic; and PA1 (2) The state of a product term line as an output line of an AND plane cannot be directly tested only by using a given circuitry for normal operation. PA1 (1) First, crosspoint generation faults in the AND plane neglected. Specifically, the empty crosspoint is disregarded as "don't care"; and PA1 (2) Then the crosspoint generation faults in the AND plane are treated. PA1 a PLA comprising an AND plane and OR plane comprising a plurality of input lines, a plurality of output lines, and a plurality of product term lines which are perpendicular to the input lines and the output lines; PA1 data providing means for providing test data to execute a test for the PLA for the AND plane during a test operation mode, and for providing normal input data for the AND plane during a normal operation mode, PA1 wherein PA1 the test data consisting of fixed data and variable data provided from the data providing means corresponds to the distribution of devices formed at crosspoints between the product term lines and the input lines. PA1 a PLA comprising an AND plane and an OR plane comprising a plurality of input lines, a plurality of output lines, and a plurality of product term lines which are grouped into at least two groups and which are perpendicular to the input lines and the output lines; PA1 selection means for selecting one of the groups; PA1 activation means for activating the selected group; PA1 data providing means for providing test data for implementing a test for each part of the PLA covered by the product term lines of each said selected group for the AND plane during a test operation mode, and for providing normal input data for the AND plane during a normal operation mode, PA1 wherein PA1 the test data consisting of fixed data and variable data provided from the data providing means corresponds to the distribution of devices formed at crosspoints between the product term lines of each said selected group and the input lines.
In the prior art, various types of PLA test methods have been proposed. These test methods are classified substantially into the following two kinds.